The present invention relates to a nonvolatile, integrated-circuit memory such as an electrically-erasable, electrically-programmable read-only-memory (EEPROM), and more particularly to an EEPROM array with memory cells that are programmed by hot-carrier injection in a region associated with each cell and that are erased by Fowler-Nordheim tunneling in another region associated with each cell, and to a method of fabricating such a device.
EEPROMs using field-effect transistors with floating-gate structures are programmed and erased by electrically storing and removing charges from the dielectric-insulated floating gates. The digital information stored in EEPROMs is read by differentiating between the source-drain impedance presented by a charged (high voltage threshold Vt) floating gate and an uncharged (low Vt) floating gate. Depending on construction, EEPROMs may be erased cell-by-cell, segment-by-segment, all cells at one time (flash-erase mode), or combinations of the foregoing.
In general, EEPROMs use one of two charge-transfer mechanisms for programming operations--either Fowler-Nordheim tunneling or hot-carrier injection. Fowler-Nordheim tunneling is generally used for erase operations. EEPROMs using hot-carrier injection programming typically employ FAMOS (Floating-gate, Avalanche-injection MOS) structures, although hot-carrier injection results from channel-hot electrons as well as avalanche breakdown (assuming NMOS).
Each of the two charge-transfer mechanisms has advantages and disadvantages in comparison to the other mechanism. Programming an EEPROM memory cell by hot-carrier injection requires lower voltage than the voltage required for Fowler-Nordheim tunneling. On the other hand, the higher voltage required for Fowler-Nordheim tunneling can be generated on-chip because of the relatively small tunneling-current required. In many cases, an additional power supply is required to meet the higher programming-current requirement for hot-carrier injection. Moreover, floating-gate erasure using hot-carrier injection of holes may cause damage to the oxide insulator layer, leading to cell degradation and failure. Use of Fowler-Nordheim tunneling for erasing causes significantly less damage to the tunnel-window oxide and is, therefore, preferable for cell durability and reliability.
EEPROMs using hot-carrier injection for programming and using Fowler-Nordheim tunneling for erasure have been described in: (a) "Electrically Alterable 8192 Bit N-Channel MOS PROM", R. Muller et al., ISSCC 1977 (p. 188-189); (b) "A Single Transistor EEPROM cell and its implementation in a 512K CMOS EEPROM", S. Mukherjee et al., IEDM 1985 (p. 616-619); (c) "An In-System Reprogrammable 256K CMOS Flash Memory", V. N. Kynett et al., ISSCC 1988 (p. 132-133); (d) "A 128K Flash EEPROM using double polysilicon Technology", G. Samachisa et al., ISSCC 1987 (p. 87-88); (e) "Reliability Performance of ETOX Based Flash Memories", G. Verma et al., IEEE/IRPS 1988 (p. 158-166); and (f) "A 90 ns 100K Erase/Program Cycle Megabit Flash Memory", V. Kynett et al., ISSCC 1989 (p. 140-141). References (b) and ((d) are also discussed in U.S. Pat. No. 4,698,787 and No. 4,639,893, respectively. References (c), (e) and (f) relate to the same cell structure. The foregoing publications include discussions of gate oxide thickness in relation to the trade-off between adequate tunneling current for erase in a reasonable time, and the impact on yields/reliability from processing defects. That is, thick gate oxide improves process yields/reliability, but reduces tunnel current, which leads to long erase times. Moreover, the junction breakdown voltage is lowered with thin gate oxide, so that, during erase, excessive junction leakage (and the unwanted generation of hot carriers) can occur before the onset of adequate Fowler-Nordheim tunnel erase current. See, e.g., references (c), (d) and (e). Thus, these EEPROMs are erased, in part, by hot holes because of low field plate breakdown voltage of the source-channel junction of the floating-gate transistor.
The approach in reference (d) uses a channel oxide of about 200 Angstroms, and uses channel-hot-electron injection for programming, and Fowler-Nordheim tunneling for erasure from the same junction. It has two disadvantages: (i) the junction optimization requirements for erasing/programming are incompatible, and cannot be met by the same junction; and (ii) a gate oxide thickness of 200 Angstroms does not allow adequate Fowler-Nordheim tunneling current for reasonable erase times with conventional 12.5V EEPROM power Supplies. On the other hand, junction-breakdown-assisted erase can occur, leading to excessive substrate current during erase.
The EEPROMs discussed in the foregoing references have not combined hot-carrier injection programming with strictly Fowler-Nordheim tunnel erasing. Using the structures described in the foregoing articles, the higher voltages required by Fowler-Nordheim tunnel erasing lead to source-channel junction field-plate breakdown, and the unwanted generation of hot carriers. U.S. patent applications Ser. No. 07/458,936 and Ser. No. 07/507,823 disclose memory cell configurations for buried-bitline-type of EEPROMs that are programmed by hot-carrier injection and that are erased by Fowler-Nordheim tunnelling. Those structures require formation of three layers of polysilicon, have buried source and drain lines, and have source/drain junctions formed by a N+ Self-Aligned Gate (NSAG) process.
Referenced U.S. patent application Ser. No. 08/082,659 also discloses a memory that is programmed by hot-carrier injection and that is erased by Fowler-Nordheim tunnelling. The cell area of the structure of that invention is characterized by a continuous buried N+ source line connected to each cell. The cell width of the structure of that invention is defined by cell-isolation thick-field insulator regions.
U.S. Pat. No. 4,422,092, issued on Dec. 20, 1983 to Daniel C. Guterman and assigned to Texas Instruments Incorporated, uses buried N+ source and drain lines to improve capacitive coupling between control gate and floating gate because of the overlap of those gates on the cell-isolation thick-field insulator regions.
U.S. patent applications Ser. No. 07/269,836; Ser. No. 07/269,837; Ser. No. 07/269,838; Ser. No. 07/269,849; and Ser. No. 07/270,594; all of which are also assigned to Texas Instruments Incorporated, utilize a three-polisilicon-layer structure with a wordline segment separate from the control gate.